1. Field of the Invention
This invention relates generally to data communication systems and methods, and more particularly to a method for maintaining timing in a CDMA rake receiver.
2. Description of the Prior Art
When using a data communication system based on bursts (packets), the generic format of a frame consists of a preamble at the beginning of each burst. Some communication protocols additionally include data and end-of-frame. The preamble is used to signify (recognize) the start of transmission. All nodes on a network traditionally use the same preamble and the same end-of-frame. Each node, therefore, is required to decode at least the beginning of the data to identify if this message is addressed to itself. Decoding efforts importantly require a real-time computational complexity. Further, traditional data communication processes are made even more complex and time consuming due to the necessity to utilize collision detection and resolve techniques.
Further, in code division multiple access (CDMA) systems, as well as others, there are overlaying coded data streams, each having its own frame timing. In view of the foregoing, it is therefore desirable to provide a technique to maintain timing in a CDMA rake receiver.
The conventional method for maintaining timing in a CDMA receiver is to let each Rake finger maintain absolute time, and count out chip, slot, and frame boundaries. Each component has its own free running counter that maintains path offset information. In this situation, the control device (usually a microcontroller or programmable DSP) then must explicitly load the path timing information obtained from the searcher hardware into each Rake finger. Since all timing is absolute, the microcontroller software must determine the values of various hardware counters that maintain finger timing.
The present invention on the other hand maintains a single counter (GCC) that tracks the chip samples as they come into the receiver; and all timing in the system is specified in terms of timing offsets from this global (or central) counter. This avoids the problem of software having to determine the hardware state of various counters that may be running at several Gigahertz speeds. All finger timings are specified in terms of offsets, and the hardware fingers use the value of the GCC counter to infer their absolute time. This eases system design, and allows a very flexible implementation of the receiver (e.g. the number of fingers can be easily scaled, the search window can be increase, etc. with minimal system level changes).
One embodiment of the present invention is more specifically directed to a system and method for maintaining timing in a CDMA rake receiver for supporting high bit rate data communication systems such as the correlator co-processor (CCP) disclosed in U.S. patent application Ser. No. 09/607,410 entitled Correlator Co-Processor For CDMA RAKE Receiver Operations, docket no. TI-30639, filed on Jun. 9, 2000, by Katherine G. Brown et al., incorporated by reference herein. The CCP is capable of receiving multiple in-phase (I) and quadrature (Q) signal samples from multiple sources to accommodate antenna diversity wherein I and Q samples may be 6-bits or more. The I and Q samples further represent multiple overlaying channels, each of which have several multi-path elements, the aggregate data rate being possibly greater than the chip rate. According to one embodiment, a hardware counter counts the incoming CDMA signal samples (or xe2x80x9cchipsxe2x80x9d). The counter is called a xe2x80x9cGlobal Chip Counterxe2x80x9d or GCC. The GCC counts modulo the period of the pseudo-noise (PN) sequence used to spread the CDMA signal. It counts the samples of the CDMA signal (xe2x80x9cchipsxe2x80x9d) as they arrive at the receiver and are written into an input buffer such as described in U.S. patent application Ser. No. 09/648,184, entitled Triple Data Buffer System for High Data Rate Communication Systems, docket no. TI-30696, filed on Aug. 25, 2000, by Katherine G. Brown, incorporated by reference herein. All timing in the CDMA receiver is then specified relative to the GCC. The searcher provides path timing, also relative to the GCC. These path timings may then be transferred to RAKE fingers. In the event that the finger allocation is performed in software, the software process does not need to know the precise timing in the hardware. Since the path timings are specified relative to GCC, the hardware can compute the precise timing by adding the relative timing value to the current value of GCC.
According to one embodiment, a method of maintaining timing in a CDMA rake receiver comprises the steps of:
a) providing a GCC counter;
b) counting via the GCC counter, CDMA signal chips as they arrive at a CDMA rake receiver;
c) generating a local pseudo-noise sequence replica of the incoming CDMA signal;
d) performing a sliding window correlation of the locally generated PN sequence replica with the incoming signal to correlate the CDMA signal timing relative to stored CDMA signal sample count values; and
e) specifying finger timing offsets relative to the stored CDMA signal sample count values to allocate RAKE fingers to the strongest multipath components.
According to yet another embodiment, a system for maintaining timing in a CDMA rake receiver comprises:
a correlator co-processor including a pseudo-noise (PN) generator for generating a PN sequence replica of an incoming CDMA signal; a Walsh code generator for generating Walsh codes; at least one chip counter (GCC) configured to count CDMA signal samples; at least one data input buffer configured to receive and store CDMA chips; a data path configured to receive and process samples of the PN sequence replica samples of the Walsh codes and CDMA chip samples; at least one task buffer configured to store a list of programmably executable tasks; an interrupt generator; at least one configuration table buffer in communication with the at least one task buffer and configured to store a plurality of configuration tables that specify how each task within the list of programmably executable tasks is implemented; at least one configuration table buffer having at least one input in communication with an external system interface bus; at least one output data buffer; and a controller in communication with the data path; and
an algorithmic software, wherein the controller in communication with the data path, the at least one task buffer, the at least one configuration table, the interrupt generator, the PN code generator, the Walsh code generator, the GCC and the at least one output buffer and directed by the algorithmic software is operational to correlate a locally generated PN sequence replica with an incoming CDMA signal such that CDMA signal timing is correlated relative to GCC chips counts and further operational to specify finger offsets relative to GCC chip counts such that RAKE fingers are allocated to the strongest multipath components.
In one aspect of the invention, a Global Chip Counter is implemented to accommodate CDMA receiver timing functions.
In still another aspect of the invention, a method is implemented to more easily maintain timing in a CDMA rake receiver.
In yet another aspect of the invention, a Global Chip Counter is implemented that allows a software process to allocate RAKE fingers to the strongest multipath components simply by specifying finger offset relative to GCC, without making an explicit reference to the current value of the time-base maintained in hardware.
Still another aspect of the invention is associated with a method that allows determination of CDMA signal parameters such as current slot number within a frame, and occurrence of slot and frame boundaries through knowledge of the current value within a Global Chip Counter and knowledge of the finger timing offset.
As used herein, xe2x80x9calgorithmic softwarexe2x80x9d means an algorithmic program used to direct the processing of data by a computer or data processing device; wherein data processing device refers to a CPU, DSP, microprocessor, micro-controller, or other like device and an interface system in which the interface system provides access to the data processing device such that data can be entered and processed by the data processing device.